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It is important to ensure that any holes in the coupon are drilled with the same tools and parameters as those on the corresponding PCB Coupons and patterns are typically used in situations where using a PCB for testing would either not provide the information required or the PCB would have to be destroyed in order to get the information Coupons and patterns can be used for microsectional analysis, electrical measurements, environmental simulation, and reliability evaluation See Fig 5111 for an example of test coupons taken from IPC-2221 (Unless noted otherwise, figures in this chapter are courtesy of the Association of Connecting Electronics Industries [IPC], and are taken from the publication IPC-600, Acceptability of Printed Circuits These figures can be found in that document under the headings noted in this chapter for specific topics Figures credited to the author of this chapter are taken from presentations made by him.

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Other figures are from the sources noted in the captions For further details on design and placement of coupons, see IPC-2221).

The process of surface micromachining begins with the deposition of the sacrificial layer onto the substrate by means of low pressure chemical vapour deposition (Figure 837) In the second step, a mask is produced to cover the surface of the sacrificial layer for subsequent etching to allow the attachment of the future cantilever beam A second mask is made to deposit polysilicon microstructural material The remaining sacrificial material is then etched away to produce the desired structure [6] Figure 838 shows the detailed view of a hinge on a micromirror produced by surface micromachining

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Microsection Microsectioning the holes from a PCB provides a cross-sectional view of the construction of the PCB. Microsectioning a PCB with a design that removes nonfunctional pads makes it virtually impossible to inspect all the interconnecting layers in the hole, so microsections are typically done on associated and optimized coupons containing PTHs that contain pads on all the layers. Microsectioning PCBs requires great skill, as the PCB contains both hard and soft materials and the area of interest is very small. Improper microsection technique can either create or hide anomalies. For example, interconnection separation can be created or hidden by improper techniques.

FIGURE 51.1 Quailty conformance test coupons taken from IPC-2221. (Courtesy of IPC.)

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An inspection lot consists of all the PCBs fabricated from the same materials, using the same processing procedures and constructions and produced under the same conditions. Differing PCBs can be combined to form an inspection lot, but then they must all be submitted together for inspection. It is the PCB manufacturer s responsibility to maintain traceability for all the PCBs in an inspection lot along with any corresponding test coupons that were separated from the production panels. The success of inspections greatly depends on how the inspection lot is formed. The goal of forming the inspection lot for a particular attribute is to allow, if applicable, a smaller sampling of the inspection lot to be representative of the entire lot. In forming inspection lots and sampling groups, the methodology for producing the attribute and the consistency of that methodology or process must be taken into consideration. Some PCB processes are done in batch form and others are done on a panel-by-panel basis. Understanding process techniques is critical in forming inspection lots and sampling groups that are representative of the product.

Sampling Inspection For some attributes, 100 percent inspection is not necessary or prudent. In these cases, a sampling of the PCBs from the inspection lot is allowed to represent the entire inspection lot. Most performance documents specify which attributes can use sampling inspection and to what extent sampling may be performed. There are many sampling plans available; the most widely known, and historically used, is MIL-STD-105, which describes an Acceptable Quality Level (AQL) for samples of an inspection lot. However, it allows a small amount of defective material to be considered acceptable and has typically been replaced by sample plans where defective parts that are found during inspection cause the lot to be termed nonconforming. This style of plan is defined as Defective Parts (C) Equals Zero (C = 0). If the inspection lot is

Fig 837: The surface micromachining procedure [16]

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